1. Field of the Invention
The invention relates in general to a Y-decoder and decoding method thereof, and more particularly to a Y-decoder, which supplies a first sensing voltage to a memory cell to be read on a memory array and successively supplies a second sensing voltage and a shielding voltage, both equal to the first sensing voltage, to the next two memory cells on the same row, and decoding method thereof.
2. Description of the Related Art
Memory devices are known in the art for storing data in a wide variety of electronic devices and applications. A typical memory device includes a number of memory cells. Often, memory cells are arranged in an array format, where a row of memory cells corresponds to a word line and a column of memory cells corresponds to a column line. Typically, the state of a memory cell is determined during a read operation by sensing the current drawn by the memory cell.
FIG. 1 is a schematic diagram of a sensing algorithm of memory cells in a conventional non-volatile memory. In FIG. 1, only one row of memory cells in one memory bank is shown for illustration convenience and each memory cell includes two bits. For example, to ascertain the current drawn by a particular memory cell A3 (specifically, the left bit of the memory cell A3), the bank-select metal oxide semiconductor (MOS) transistor sel2 is turned on to select the column line CL2 and supply a ground voltage G to the source of the memory cell A3 via the metal bit line MBL2 and the column line CL2. At the same time, the bank-select MOS transistor sel3 is turned on to select the column line CL3 and supply a sensing voltage (or drain voltage) D1 to the drain of the memory cell A3 via the metal bit line MBL3 and the column line CL3.
Typically, due to an array effect, a by-pass current Ib will flow by the next memory cell A4 and result in a smaller and incorrect sensing current Is flowing to a sense amplifier (not shown) via the metal bit line MBL3. In order to reduce the by-pass current Ib such that the sensing current Is of the sense amplifier can be closer to the cell current Ic of the memory cell A3, the bank-select MOS transistor sel4 is simultaneously turned on to select the column line CL4 and supply a shielding voltage S1, which is substantially equal to the sensing voltage D1, to the drain of the next memory cell A4 via the metal bit line MBL0 and the column line CL4, and the drains of the following memory cells A5, A6, . . . are all controlled to float (F).
However, in practical circuit design, it is difficult to supply the shielding voltage S1 having a value very close to the sensing voltage D1 due to inherent circuit coupling and interference. As a result, an amount of bypass current Ib (about 15% of the cell current Ic) still occurs to make the sensing current Is smaller than the cell current Ic (only 85% of the cell current Ic), thereby narrowing the cell operating window and reducing the cell program speed of the non-volatile memory.